基于FPGA的高阶高速FIR滤波器设计与实现  

The Design and Realization of High-tap Filters Based on FPGA

作　　者：赵文亮[1] 蒋冰[1] 

机构地区：[1]电子科技大学,四川成都610054

出　　处：《中国有线电视》2006年第3期329-331,共3页China Digital Cable TV

摘　　要：提出了一种基于FPGA的高阶高速FIR滤波器的设计与实现方法。通过一个169阶的均方根升余弦滚降滤波器的设计,介绍了如何应用流水线技术来设计高阶高速FIR滤波器,并且对所设计的FIR滤波器性能、资源占用进行了分析。This paper proposes the design and realization of high-tap, high-speed filters based on FPGA. The technique how to use pipeline architecture to design high speed FIR filters is illustrated through the process of designing a 169 -tap square root raised cosine （SRRC）FIR digital filter which has the characteristic of linear phase. The analysis of the filter performance and the resource consumed by the filter is also made in this article.

关 键 词：CSD FIR滤波器 流水线结构 FPGA 

分 类 号：TN713[电子电信—电路与系统]