基于数据切片的系统芯片测试控制技术研究  

Study on Test Control for System-on-a-Chip Based on Test Data Slicing

作　　者：王党辉[1] 樊晓桠[1] 高德远[1] 张盛兵[1] 安建峰[1] 

机构地区：[1]西北工业大学航空微电子中心,陕西西安710072

出　　处：《测试技术学报》2006年第3期195-200,共6页Journal of Test and Measurement Technology

基　　金：国家自然科学基金资助项目(60276046);陕西省自然科学基金资助项目(2005F47);十五预研资助项目(41308010308);西北工业大学青年教师基金资助项目(M016205)

摘　　要：在基于总线结构的系统芯片测试中，提出了在考虑扫描控制信号的条件下，采用测试数据切片的测试控制方式来降低测试调度的粒度．从而提高测试访问机制带宽的利用率．并给出了在这种控制方式下测试时间的下限值．最后采用VCS仿真器在Benchmark ITC’02中若干电路上对提出的测试控制方法进行仿真实验．结果显示：相对于文献[KumarS．MarinssenEJ．Control—AwareTestArchitectureDesignforModularSoCTesting[C]．IEEEProceedingsof8thEuropeanTestWorkshop，Maastricht，TheNetherlands：IEEECS．2003：57—62．]中考虑了测试控制的最优结果．测试时间要缩短约12．OO％～21．90％；另外，相对于其它文献中不考虑测试控制的结果，测试时间还要缩短大约1．82％～30．40％．Improving the usage of the test access mechanism＇s bandwidth is a main goal of the SoC test scheduling. Based on the bus-architecture, a novel method is proposed which slices test data into small blocks to reduce the granularity of the test schedule. It also takes account of the control problem of the scan chains. The proposed method is applied to several circuits of ITC＇02 Benchmark by VCS simulator. The results show that the total test time can be reduced about 12.00%～21.90% compared with the best result of the reference [Kumar S, Marinssen E J. Control-Aware Test Architecture Design for Modular SoC Testing [C]. IEEE Proceedings of 8th European Test Workshop, Maastricht, The Netherlands： IEEE CS, 2003：57-62. ] which takes account of the test controlling. In addition, the total test time can be further reduced about 1.82%～30.40% compared with the results of other methods which do not take into account the test controlling.

关 键 词：数据切片 测试 系统芯片 测试调度 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]