MICROTHREAD BASED (MTB) COARSE GRAINED FAULT TOLERANCE SUPERSCALAR PROCESSOR ARCHITECTURE  

作　　者：Fu Zhongchuan Chen Hongsong Cui Gang 

机构地区：[1]Fault Tolerance Computing Laboratory, Department of Computer Science and Technology, Harbin Institute of Technology, Harbin 150001, China [2]Parallel Architectures and Compilation Techniques Group, Department of Computer Science and Technology, Harbin Institute of Technology, Harbin 150001, China

出　　处：《Journal of Electronics(China)》2006年第3期461-466,共6页电子科学学刊（英文版）

摘　　要：Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance. This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based (MTB) coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations.Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance. This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based （MTB） coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations.

关 键 词：Microthread Basic block Coarse grained fault tolerance Superscalar processor 

分 类 号：TN4[电子电信—微电子学与固体电子学]