一种参数可动态智能设置的全数字锁相环路  

A full-digital phase-locked loop(PLL) with dynamic parameter intelligent setting

作　　者：熊卓列[1] 张深基[1] 

机构地区：[1]湖南工程学院电气与信息工程系,湖南湘潭411101

出　　处：《陕西理工学院学报（自然科学版）》2006年第2期10-13,共4页Journal of Shananxi University of Technology:Natural Science Edition

摘　　要：在采用FPGA可编程技术实现的全数字锁相环路芯片中,通过使用VHDL硬件描述语言增加锁相环状态检测功能模块,能实现对锁相环工作状态(失锁或锁定)的检测。在片外设置一CPU对锁相环状态检测模块输出的状态信号进行检测,同时依据检测结果对不同状态下环路滤波器中可逆计数器模值进行动态智能设置,能实现锁相环路在失锁时快速进入锁定状态,在锁定时消除相位抖动和提高对噪声的抑制能力,从而达到改善输出频率质量的目的。Through VHDL hardware description language and increasing state detection of function module in PLL, the detection of working state of PLL （ out of lock or lockage） can be realized in the chip of all-digitized phase lock loop realized by FPGA programmable technology. Designing CPU out of chip to detect the delivered status signal of state detection module in PLL, meanwhile, based on the detected results, carrying on intelligently dynamic design of the reversible counter＇s amplitude under different states of loop electric filter, it can realize the fast lockage state in case of the loose lock in PLL, the removal of phase jitter, and the capacity to inhibit noise. Thus, the quality of output frequency can be improved.

关 键 词：FPGA 全数字锁相环路 VHDL语言 锁相状态检测 

分 类 号：TN742.1[电子电信—电路与系统]