一种抗衰落的位同步设计和FPGA实现  

Design and FPGA Implementation of a Anti-fading Bit Synchronization Method

作　　者：刘丽哲[1] 张德华[2] 

机构地区：[1]中国电子科技集团公司第54研究所,河北石家庄050081 [2]河北省人民政府信息化工作办公室,河北石家庄050071

出　　处：《无线电工程》2006年第6期57-58,共2页Radio Engineering

摘　　要：在中低速散射通信中,调制解调器的位同步信号通常从含有同步信息的包络中提取。为了保证同步信号的信噪比,采用上述方法需要耗费大量FPGA资源。基于此,提出并分析了一种简单易行的抗衰落同步方法,即“飞轮”同步法。不但详细描述了该方法的算法原理,而且还用FPGA技术通过VHDL硬件描述语言编程实现了该位同步提取方案。In the troposcatter communication at low rate or medium rate, a bit synchronization used by modem is usually extracted from the envelope that contains synchronization information. To guarantee the SNR of synchronization signal, it needs a great lot of FPGA resource for adopting the previous method. For this problem, we proposes and analyses an anti-fading synchronization method, named as flywheel, which is simple and implemented easily. This paper not only makes a detail description of the arithmetic theory of this method, but also realizes the bit synchronization scheme with FPGA by VHDL programming.

关 键 词：位同步 FPGA 最大值 中低速散射通信 

分 类 号：TN911[电子电信—通信与信息系统]