基于SoC设计的软硬件协同验证方法学  

Methodology of SoC Design using Hardware/Software Co-simulation

作　　者：赵刚[1] 侯立刚[1] 刘源[1] 朱修殿[1] 吴武臣[1] 

机构地区：[1]北京工业大学电子科学与信息系,北京100022

出　　处：《微电子学与计算机》2006年第6期24-26,共3页Microelectronics & Computer

摘　　要：文章介绍了软硬件协同验证方法学及其验证流程。在软件方面,采用了一套完整的软件编译调试仿真工具链,它包括处理器的仿真虚拟原型和基本的汇编、链接、调试器;在硬件方面,对软件调试好的应用程序进行RTL仿真、综合,并最终在SoC设计的硬件映像加速器(FPGA)上实现并验证。This paper presents a hardware/software co-simulation framework enabling fast prototyping in system-onchip designs. On the software side, a complete tool suite consisting of fast compiled processor simulator, assembler, linker and debugger are used to debug the software design. On the hardware side, Real software execution is implemented as the event driver in a testhench and continued on a fast prototype to increase simulation speed and hardware functional validity.

关 键 词：软硬件协同验证 FPGA综合 

分 类 号：TN47[电子电信—微电子学与固体电子学]