基于门控时钟技术的低功耗三值D型触发器设计  

A low-power ternary D-type flip-flop design based on clock-gating technique

作　　者：叶锡恩[1] 陶伟炯[1] 王伦耀[1] 

机构地区：[1]宁波大学电路与系统研究所,浙江宁波315211

出　　处：《电路与系统学报》2006年第3期106-109,共4页Journal of Circuits and Systems

基　　金：国家自然科学基金资助项目(60273093)

摘　　要：本文在三值D型触发器的基础上提出了一种低功耗三值门控时钟D型触发器的设计。该设计通过抑制触发器的冗余触发来降低功耗,PSPICE模拟验证了该触发器具有正确的逻辑功能。与三值D触发器相比,该触发器在输入信号开关活动性较低的情况下具有更低的功耗。同时该电路结构可以推广到基值更高的低功耗多值触发器的设计中。Based on ternary D-type flip-flop, a low-power ternary clock-gating D-type flip-flop is proposed. The proposed design reduces power dissipation by restraining the redundant triggered actions of the flip-flop. PSPICE simulation shows that this flip-flop has a correct logic function. Compared with ternary D-type flip-flop, this design reduces power dissipation significantly when input signals have low switching activity. Furthermore, the proposed construction can be extended to the design of multiple valued flip-flops with a higher radix easily.

关 键 词：低功耗 门控时钟 触发器 多值逻辑 

分 类 号：TN432[电子电信—微电子学与固体电子学] TP331[自动化与计算机技术—计算机系统结构]