高速、可配置RSA密码协处理器的VLSI设计  

VLSI Design of a High-Speed RSA Crypto-Coprocessor with Reconfigurable Architecture

作　　者：范益波[1] 曾晓洋[1] 于宇[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《计算机研究与发展》2006年第6期1076-1082,共7页Journal of Computer Research and Development

基　　金：国家"八六三"高技术研究发展计划基金项目(2003AA1Z1270);上海市科委重大攻关基金项目(03dz15001)~~

摘　　要：通过算法级分析和对比RSA原始算法以及改进型模幂模乘算法,提出了一种双重流水线结构的RSA密码协处理器体系结构,该结构具备高速、可配置性能·基于该体系结构,可以根据不同的用户需求,方便地设计出支持各种速度和密钥长度的RSA密码处理器·该体系结构尤其适用于设计高速、高位宽RSA密码芯片;同时其可配置性能也可以满足低速、高位数、高安全性RSA系统的市场需求·另外,基于该体系结构设计的RSA加密IP,非常适合SoC的芯片设计·最后,基于该体系结构设计了一款高速1024b RSA密码加密芯片,采用0·18μm标准单元库设计,实现结果显示,芯片在150MHz时钟频率下能完成每秒5000次1024b RSA加密运算,是国内同类产品中速度最快的·Through analyzing and comparing the normal RSA algorithm to the modified modular exponentiation and Montgomery multiplication algorithm in the arithmetic level, a nested pipelined RSA crypto-processor architecture is presented. This architecture has high-speed and reconfigurable feature. Based on the architecture, an RSA crypto-processor with various speed ＆ key size can be designed, and it is especially valuable for high speed, long key size applications. It is also suitable for low speed, long key size, and high security level applications, or configured as an IP core embedded in SoC platform. As an example, a high-speed 1024-bit RSA crypto-processor is implemented using 0.18μm CMOS technology. The simulation result indicates that the encryption rate of the crypto-processor is more than 5000 times per second at 150MHz clock frequency. The performance of the crypto-processor proposed is the best reported in the literature in China.

关 键 词：RSA 高速 可配置 加密芯片 VLSI 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]