基于FPGA的异步FIFO设计与实现  

Asynchronous FIFO Design and Implementation Based on FPGA

作　　者：熊红兵 陈琦[2] 

机构地区：[1]清华大学电子工程系 [2]中国科学院电子学研究所

出　　处：《微计算机信息》2006年第06Z期216-218,共3页Control & Automation

摘　　要：异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷(GRAY)变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点,使得整个系统可靠性高和抗干扰能力强,系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构,使得系统具有良好的可扩充性。Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray （Only one bit changes between neighboring two clock ） improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.

关 键 词：FWO 双口RAM 格雷码 指针解释 指针生成 

分 类 号：TN317[电子电信—物理电子学]