一种高效的低功耗取指与预解码单元的设计  

Design of Instruction Fetch & Pre-decode Unit for High Performance and Low Power

作　　者：陈亮[1] 陈健[1] 

机构地区：[1]上海交通大学微电子学院DSP教研室,上海200030

出　　处：《小型微型计算机系统》2006年第7期1262-1265,共4页Journal of Chinese Computer Systems

基　　金：国家"八六三"项目(2003AAIZ)资助.

摘　　要：在数字信号处理芯片中,取指单元的效率对芯片性能有非常大的影响.提出一种新的并行处理结构以及门控时钟电路,讨论这些结构的优点,并提出几种优化方法,在提高效率的同时,极大降低了功耗开销.In the field of Digital Signal Processor design , the efficiency of the Intruction Fetch Unit has a great impact on the chip＇s performance. This paper proposed a novel parallel architecture and clock-gating circuit. The advantages were discussed . Some optimzation methods were proposed too, which greatly reduced the power consumption while enhanced the performace.

关 键 词：并行处理 门控时钟 指令队列 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]