Low complexity reconfigurable architecture for the 5/3 and 9/7 discrete wavelet transform  

作　　者：Xiong Cheng yi Tian Jinwen Liu Jian 

机构地区：[1]Coll. of Electronic Information Engineering, South Center Univ. for Nationalities, Wuhan 430074, P.R. China [2]Inst. of Pattern Recognition & Artificial Intelligence,Key Lab. of Education Ministry for Image Processing and Intelligent Control, Huazhong Univ. of Science & Technology, Wuhan 430074, P.R. China

出　　处：《Journal of Systems Engineering and Electronics》2006年第2期303-308,共6页系统工程与电子技术（英文版）

摘　　要：Efficient reconfigurable VLSI architecture for 1-D 5/3 and 9/7 wavelet transforms adopted in JPEG2000 proposal, based on lifting scheme is proposed. The embedded decimation technique based on fold and time multiplexing, as well as embedded boundary data extension technique, is adopted to optimize the design of the architecture. These reduce significantly the required numbers of the multipliers, adders and registers, as well as the amount of accessing external memory, and lead to decrease efficiently the hardware cost and power consumption of the design. The architecture is designed to generate an output per clock cycle, and the detailed component and the approximation of the input signal are available alternately. Experimental simulation and comparison results are presented, which demonstrate that the proposed architecture has lower hardware complexity, thus it is adapted for embedded applications. The presented architecture is simple, regular and scalable, and well suited for VLSI implementation.Efficient reconfigurable VLSI architecture for 1-D 5/3 and 9/7 wavelet transforms adopted in JPEG2000 proposal, based on lifting scheme is proposed. The embedded decimation technique based on fold and time multiplexing, as well as embedded boundary data extension technique, is adopted to optimize the design of the architecture. These reduce significantly the required numbers of the multipliers, adders and registers, as well as the amount of accessing external memory, and lead to decrease efficiently the hardware cost and power consumption of the design. The architecture is designed to generate an output per clock cycle, and the detailed component and the approximation of the input signal are available alternately. Experimental simulation and comparison results are presented, which demonstrate that the proposed architecture has lower hardware complexity, thus it is adapted for embedded applications. The presented architecture is simple, regular and scalable, and well suited for VLSI implementation.

关 键 词：VLSI discrete wavelet transform lifting scheme embedded decimation reeonfigurable. 

分 类 号：TN47[电子电信—微电子学与固体电子学]