基于FPGA快速同步算法的研究  

Research of Rapid Synchronization Algorithm Based on FPGA

作　　者：施玉松[1] 李维英[1] 邢成文[1] 

机构地区：[1]西安电子科技大学宽带无线通信实验室,西安710071

出　　处：《北京电子科技学院学报》2006年第2期32-35,共4页Journal of Beijing Electronic Science And Technology Institute

摘　　要：本文提出了一种基于FPGA的快速同步捕获方案,该方案采用相关峰尖锐的巴克码组作为帧头,帧同步捕获的同时实现位同步。仿真结果表明,该算法能够迅速实现位同步的捕获,且位定时抖动小,在信噪比较低的条件下仍有较好的性能。实际中将其应用于π/4-DQPSK调制方式,流水线结构,在ALTERA公司的FPGA芯片cycloneⅡ上实现。In this paper, a new rapid synchronization algorithm based on FPGA is proposed, which can accomplish symbol timing and frame synchronization synchronously. The simulation result indicates that this algorithm can capture rapid symbol timing and slight time jitter;, it also does well under low SNR. In practice, π/4-DQPSK is chosen as the pivot of our research, and the implementation is achieved in cyclone Ⅱ with pipelining structure.

关 键 词：同步 Π/4-DQPSK 流水线 FPGA 

分 类 号：TN914.3[电子电信—通信与信息系统]