网络处理器的线程级并行技术研究  

Thread Level Parallel Processing Research for Network Processor

作　　者：周昔平[1] 高德远[1] 樊晓桠[1] 张盛兵[1] 徐邦海[1] 

机构地区：[1]西北工业大学航空微电子中心,陕西西安710072

出　　处：《微电子学与计算机》2006年第7期34-38,共5页Microelectronics & Computer

基　　金：国防"十五"预研课题(41308010307)

摘　　要：线程级并行技术能有效的提高微处理器内核的资源利用率,是目前高性能微处理器研究的重点内容。文章分析了网络处理器的线程级并行技术中存在的几个关键问题,结合网络协议处理的特征提出了一种适合于网络协议处理的混合多线程结构。并将其成功应用于网络协议处理微引擎NRS05的设计中,最大程度的提高了网络处理器的分组吞吐率。Thread level parallel processing is one of the key technologies for modem processor design, which improves the processor performance and resource utilization effectively. This paper gives a detail analysis for some key problems of thread level parallel processing in network processor design. And a novel mixed-grained multi-threading architecture is presented according to the packet processing character. It is efficient for hiding long latency operations and coping with pipeline stars. This multi-threading architecture is implemented in the design of a network processing micro-engine, called NRS05, and processor resource utilization is maximized in this micro-engine.

关 键 词：多线程 网络处理器 线程现场 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]