A UNIVERSAL ALGORITHM FOR PARALLEL CRC COMPUTATION AND ITS IMPLEMENTATION  

作　　者：Xu Zhanqi Yi Kechu Liu Zengji 

机构地区：[1]State key Lab on ISN, Xidian University, Xi＇an 710071, China

出　　处：《Journal of Electronics(China)》2006年第4期528-531,共4页电子科学学刊（英文版）

基　　金：Supported by the National Natural Science Foundation of China (No.60172029) and the Natural Science Foun-dation of Shaanxi Province (No.2004F04).

摘　　要：Derived from a proposed universal mathematical expression, this paper investigates a novel algo-rithm for parallel Cyclic Redundancy Check (CRC) computation, which is an iterative algorithm to update the check-bit sequence step by step and suits to various argument selections of CRC computation. The algorithm proposed is quite suitable for hardware implementation. The simulation implementation and performance analysis suggest that it could efficiently speed up the computation compared with the conventional ones. The algorithm is implemented in hardware at as high as 21Gbps, and its usefulness in high-speed CRC computa-tions is implied, such as Asynchronous Transfer Mode (ATM) networks and 10G Ethernet.Derived from a proposed universal mathematical expression, this paper investigates a novel algorithm for parallel Cyclic Redundancy Check （CRC） computation, which is an iterative algorithm to update the check-bit sequence step by step and suits to various argument selections of CRC computation. The algorithm proposed is quite suitable for hardware implementation. The simulation implementation and performance analysis suggest that it could efficiently speed up the computation compared with the conventional ones. The algorithm is implemented in hardware at as high as 21Gbps, and its usefulness in high-speed CRC computations is implied, such as Asynchronous Transfer Mode （ATM） networks and 10G Ethernet.

关 键 词：Cyclic Redundancy Check （CRC） Parallel computation Multi-bit divider 

分 类 号：TN91[电子电信—通信与信息系统]