2．56 Gbps对称密码芯片的设计与实现  

Design and Implementation of a Symmetric Key Data Encryption/Decryption IC with 2.56 Gbps Throughput

作　　者：金永明[1] 戎蒙佸 朱甫臣[1] 吕永其[1] 

机构地区：[1]上海交通大学电子信息与电气工程学院,上海200030

出　　处：《计算机工程》2006年第14期238-240,共3页Computer Engineering

基　　金：国家"863"计划基金(2003AA141040)

摘　　要：根据国家信息安全领域确定的密码标准体系自行设计的对称密码算法,提出了一种高速对称密码芯片结构。芯片中加解密核心部件用流水线实现,密钥生成采用电路复用技术,兼顾了芯片的速度和面积。并提出了一种改进的二元决策电路,以实现字节替换函数,有效地减小了关键路径的时延。芯片采用中芯国际0．18μm CMOS工艺标准单元库流片成功,支持3种密钥长度和4种工作模式,可以稳定工作在80MHz,吞吐量达到2．56Gbps。This paper introduces a high speed symmetric key data encryption/decryption IC according to the algorithm which is designed on the basis of encryption standards established by the national information security domain. In order to balance the sPeed and the area of the chip, the algorithm uses pipeline structures to realize the core and non-pipeline circuits to design the key expansion module. It also introduces the improved binary decision circuits to realize the byte substitution function so that the critical path delay is significantly reduced. The design is implemented in a 0.18μm CMOS standard cell library of SMIC and successfully fabricated. The chip, which supports three different lengths of key and four working modes, runs steadily at a maximum 80MHz, the data throughput is up to 2.56 Gbps.

关 键 词：对称密码 二元决策图 专用集成电路 

分 类 号：TP393.08[自动化与计算机技术—计算机应用技术]