新型全数字锁相环的逻辑电路设计  

A Logic Circuit Design of All Digital Phase-Locked Loop

作　　者：徐健飞[1] 庞浩[1] 王赞基[1] 陈建业[1] 

机构地区：[1]清华大学电机工程与应用电子技术系,北京市海淀区100084

出　　处：《电网技术》2006年第13期81-84,共4页Power System Technology

摘　　要：设计出一种新型全数字锁相环(enhancedphase-lockloop,EPLL)的逻辑电路。该电路基于轨迹跟踪原理实现与交流基波成分的同步,其锁相速度快,精度高。同时,为兼顾锁相速度和稳定性的设计要求,提出调节EPLL动态参数的新方法,获得具有优化结构的全数字锁相逻辑电路。锁相跟踪实验验证了该锁相环技术的性能,证实了其在提取和分析谐波方面的有效性。An all-digital enhanced phase-lock loop （EPLL） technology based on ADC and FPGA is designed, On the basis of principle of trajectory tracking EPLL realizes the synchronization with AC fundamental harmonic component, the phase-lock speed of EPLL is rapid and its accuracy is satisfactory. To meet the design requirement of phase-lock speed and stability simultaneously, a new method to adjust dynamic parameters of EPLL is put forward, thus an all-digital phase-lock logical circuit with optimized structure is obtained. The results of phase-lock tracking test verify the performance of EPLL, and the effectiveness of EPLL in harmonics extraction and analysis is confirmed.

关 键 词：全数字锁相环 动态参数调节 同步 数字逻辑电路 

分 类 号：TM715[电气工程—电力系统及自动化]