并行帧同步扰码器的扩充比特设计法  

A Extension Bit Method for Parallel Frame Synchronous Scrambler

作　　者：张羿猛[1] 黄芝平[1] 毕占坤[1] 王跃科[1] 

机构地区：[1]国防科技大学机电工程与自动化学院仪器系,长沙410073

出　　处：《光子学报》2006年第7期1048-1051,共4页Acta Photonica Sinica

基　　金：国防预研基金资助项目

摘　　要：在递推公式并行扰码处理方法的基础上,提出了一种使用扩充比特进行帧同步扰码器设计的新方法·利用扰码序列的周期性原理,从理论上证明了并行扰码复杂度与扰码生成多项式的具体形式无关·无需计算并行扰码递推公式,简化了解扰码器的设计过程,只须用深度与生成多项式阶数相关的存储器和少量的读写控制逻辑就可以实现对任意字宽解扰码处理·该方法在FPGA设计与实现中得到了验证,实现了高效和低复杂度.采用该方法的处理模块已在光通信传输网前端处理系统中得到了应用·Based on parallel recursive synchronous scramble method, an novel extension bit method for parallel frame synchronous scrambler is proposed. Using periodicity of the scramble sequence, it is theoretic proved the complexity of this method is not depended on the expression of generation polynome. This method does not need to calculate recursive formula of the parallel scrambler. It makes the design of scrambler and descrambler simple. The memory depth of scramler is only relative to the rank of the generation polynome. The arbitrary word-wide scrambler can be constitute with the memory a few read/ write logic. It is high efficence and low logical complexity proved by FPGA designing, and this mothed has been applied in the front terminal of high-speed optical transport system.

关 键 词：并行扰码 扩充比特法 SDH传输网 

分 类 号：TN929.11[电子电信—通信与信息系统]