H.264/AVC中去块效应滤波系统的结构设计  

Architecture Design for Deblocking Loop Filter System in H.264/AVC

作　　者：谢将相[1] 杨昆[1] 张春[1] 王志华[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《电视技术》2006年第7期28-30,34,共4页Video Engineering

摘　　要：针对H.264/AVC解码器中的去块效应滤波系统提出了一种有效的VLSI硬件结构。该系统是基于OR1200处理器挂于Wishbone总线上,采用UMC0.18CMOS工艺流片。该系统较以往去块效应滤波系统具有高效率低复杂度等特点。由仿真综合结果可知,该系统在工作频率100MHz时对HDTV(1920×1088@29fps;1280×720@66fps)能较好实现实时滤波,并且综合后的逻辑门只有15.33k(不含片内SRAM)。This paper proposes an efficient VLSI hardware architecture of deblocking filter in H.264/AVC decoder. This system, which is based on OR1200 CPU, is attached to the Wishbone bus and tapeouted by UMC0.18 CMOS technology. This system is better than others in high-efficiency and low-complexity. Simulation results show that our system can easily support real-time deblocking of HDTV video application（1 920×1 088@29 Hz;1 280×720@66 Hz） when working at 100 MHz. And, the synthesized logic gate count is only 15.33 k （not including on-chip SRAM）.

关 键 词：H.264标准 去块效应滤波系统 块效应 WISHBONE总线 

分 类 号：TN764[电子电信—电路与系统]