视频处理器软硬件协同设计  

Video processor design using hardware and software co-design strategy

作　　者：俞国军[1] 刘鹏[1] 姚庆栋[1] 蒋志迪[1] 蔡卫光[1] 

机构地区：[1]浙江大学信息与电子工程学系,浙江杭州310027

出　　处：《浙江大学学报（工学版）》2006年第7期1117-1122,共6页Journal of Zhejiang University：Engineering Science

基　　金：国家"863"高技术研究发展计划资助项目(2002AA1Z1140);霍英东青年教师奖优选课题资助项目(94031)

摘　　要：为了提高视频图像处理速度与硬件资源利用,针对一种基于精简指令集处理器与数字信号处理器(RISC/DSP)混合体系结构的媒体处理器:浙大数芯(MD32),给出了一种软硬件协同设计策略.所给策略结合视频处理核心算法,研究分析MPEG视频编码标准的处理过程,进行了视频处理指令扩展设计,提高了数据的并行处理能力,利用了指令内并行执行特性.为有效实现扩展指令,处理器执行级采用了可扩展流水级技术.实验结果表明,指令扩展硬件成本仅占MD32的2.7%,逆离散余弦变换实现性能比MMX/SSE指令集实现的性能分别提高31%和23%,运动补偿性能比MMX指令集实现的性能提高了40%.A hardware/software co-design method for video processing instruction extension based on microprocessor MediaDSP3201 （briefly, MD32） with unifying architecture of reduced instruction set computer and digital signal processor （RISC/DSP） was introduced to improve video image processing speed and utilization of hardware resource. The key algorithm in video processing was analyzed based on MPEG video coding standard. The proposed method improved the parallelism for data processing and utilized parallel processing characteristics within instructions. In the instruction execution pipeline stage, scalable pipeline technology was adopted to realize the video processing instruction. Results showed that hardware cost for the instruction extension was 2.7%, and that performance improvement achieved was 31% and 23% respectively compared to MMX/SSE for inversed discrete cosine transform （IDCT） and 40% for motion compensation （MC） compared to MMX.

关 键 词：视频处理器 视频压缩 协同设计 单指令多数据 

分 类 号：TP37[自动化与计算机技术—计算机系统结构] TN919.81[自动化与计算机技术—计算机科学与技术]