用原理图法在单片CPLD上实现六位数字频率计  

Implementation of Digital Frequency Meter Based on Single CPLD Device Using Schematic Method

作　　者：沈祖斌[1] 

机构地区：[1]江汉大学数学与计算机科学学院,湖北武汉430056

出　　处：《计算机测量与控制》2006年第7期959-961,共3页Computer Measurement &Control

基　　金：武汉市科技计划资助项目(20015007090)。

摘　　要：在阐明了EDA(电子设计自动化)工具各种常用的输入方法：原理图设计输入方法,硬件描述语言设计输入方法,有限状态机的设计输入方法,以及它们之间的特点的基础上,讨论了EDA设计输入方法对基于CPLD器件设计实现的影响,并详细地给出了在ALTERA公司的单片CPLD器件EPM7064上实现六位数字频率计的原理图设计方法,最后对设计的综合性能报告进行了分析比较。This paper describes clearly the various design entry tools of electronic design automation （abbreviated EDA） ： schematic design entry tools, hardware description language design entry methods, finite state machine design entry tools, and the different features between them. The paper discusses the influence on design implementation based on ALTERA corporation＇ s single chip CPLD device through using different EDA design entry methods. A realization of the 6--bit digital frequency meter based on a single CPLD device EPM7064 is given in detail by using the schematic design entry method. The paper finally compares and analyzes the overall performance of the design through the EDA tool＇ s project reports.

关 键 词：数字频率计 CPLD 原理图设计输入 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构] TP317[自动化与计算机技术—计算机科学与技术]