Full-Chip Scalable Routing Framework Considering Congestion and Performance  

考虑拥挤度和性能的全芯片可控布线系统框架(英文)

作　　者：姚海龙[1] 蔡懿慈[1] 洪先龙[1] 周强[1] 

机构地区：[1]清华大学计算机科学与技术系,北京100084

出　　处：《Journal of Semiconductors》2006年第7期1201-1208,共8页半导体学报（英文版）

基　　金：国家高技术研究与发展计划资助项目(批准号:2005AA1Z1230)~~

摘　　要：This paper presents a novel full-chip scalable routing framework that simultaneously considers the routing congestion and the circuit performance. In order to bridge the gap, the presented framework calls the detailed router immediately after a global route is extracted. With the interleaving mode of global routing immediately followed by detailed routing, accurate routing resource and congestion information can be obtained, which provides valuable guidance for the following global routing process. The framework features the fast pattern and framed shortest path global router,a maze-based congestion-driven detailed router, and better interaction between the two routers. In the framework, timing critical nets can be assigned higher priority for performance concern, and different net ordering techniques can be adopted for different routing objectives. The framework is tested on a set of commonly used benchmark circuits and compared with a previous multilevel routing framework. Experimental results show that the presented framework obtains significantly better routing solutions than the previous one considering circuit performance, routing completion rate, and runtime.提出一个全新的全芯片可控布线系统框架,同时考虑布线拥挤度和芯片性能.为了在总体布线和详细布线之间架起桥梁,该框架把总体布线和详细布线集成起来,交互进行,每完成一个线网的布线,都及时对布线资源进行更新,由此可以得到精确的资源估计结果,有利于指导后续总体布线决策.该系统框架的主要特征包括快速的基于模式的和基于外框约束下最短路算法的总体布线器、基于迷宫算法的拥挤度驱动的详细布线器以及在两个布线器之间很好的交互性.在该布线系统框架中,为了优化电路性能,在布线中关键线网被赋予更高的优先级.同时,为了优化不同的布线目标,可以采用不同的线网排序策略.该布线系统框架在一套公用的测试电路上完成测试,并与之前提出的多级布线系统框架进行比较,实验结果表明,文中提出的布线系统框架在电路性能、布通率和运行时间方面都取得了很大改进.

关 键 词：CONGESTION multilevel routing PERFORMANCE scalable routing 

分 类 号：TN47[电子电信—微电子学与固体电子学]