一个用于14位采样保持电路的全差分增益增强放大器的分析和设计  

Analysis and Design of Fully Differential Gain-boosted OPAMP Dedicated to 14 bit Sample-and-Hold Circuit

作　　者：杨鑫[1] 李挥[1] 

机构地区：[1]北京大深圳研究生院信息学院,广东深圳518055

出　　处：《现代电子技术》2006年第16期1-3,6,共4页Modern Electronics Technique

基　　金：2005年粤港关键领域重点突破项目资助(2005A10208004)

摘　　要：介绍了一种全差分增益增强CMOS运算放大器的设计和实现。该放大器用于14位20 MHz采样频率的流水线模/数转换器(A/D)的采样保持电路。为了实现大的输入共模范围,采用折叠式共源共栅放大器。主放大器采用开关电容共模反馈电路在获得大输出摆幅的同时降低了功耗。辅助放大器则采用简单的连续时间共模反馈电路。该放大器采用UMC Logic 0.25μm工艺,电源电压为2.5 V。Hspice仿真结果显示,在负载为15 pF的情况下,其增益为104 dB,单位增益带宽为166 MHz。In this paper,a high DC gain,gain- boosted fully differential CMOS operational amplifier is designed. It is used for the Sample and Hold （S ＆ H） circuits of a 14 b 20 MHz pipeline A/D convertor. The main amplifier is folded-cascode to obtain a large range of input common mode voltage. Used the switched capacitor Common Mode Feedback circuit （CMFB） in main amplifier to achieve a large output voltage swing and decrease the static power consumption at the same time. A simple continuous time CMFB is implemented in the auxiliary amplifier to reduce power consumption and simplify the circuit. The amplifier is designed in UMC 0.25 μm logic CMOS process with 2.5V power supply. Hspice simulation shows that the amplifier has the DC gain of 104dB and the unity gain bandwidth of 166 MHz under 15 pF load.

关 键 词：CMOS 增益增强 开关电容共模反馈 模/数转换电路 

分 类 号：TN721.1[电子电信—电路与系统]