高速Berlekamp-Massey算法结构及电路实现  

High-speed architecture and implementation for Berlekamp-Massey algorithm

作　　者：张军[1] 王志功[1] 胡庆生[1] 肖洁[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,江苏南京210096

出　　处：《电路与系统学报》2006年第4期85-89,124,共6页Journal of Circuits and Systems

摘　　要：介绍了两种用于二进制BCH解码器的高速Berlekamp-Massey算法实现方案。在加入寄存器以减少关键路径的延时从而提高电路速度的基础上,一种方法是采用有限域乘法器复用的方法降低电路的复杂度;另一种方法则通过对有限域乘法器进行流水线设计,进一步提高电路的工作速度,实现超高速应用。设计中充分利用了二进制BCH码中Berlekamp-Massey算法迭代计算时修正值间隔为零的性质,用超前计算的方法减少了运算周期的增加。提出的方案可用于设计高速光通信系统的信号编解码芯片。Two high-speed architectures of Berlekamp-Massey algorithm for binary BCH codes are presented in this paper. Based on inserting a register in critical paths to accelerate the circuits operating speed, one improved method is that the circuit complexity can be reduced by sharing the finite field multiplier. The operating speed can be further increased by pipelining the finite field multiplier. For binary BCH codes, the discrepancy is always zero on even-number iterations. This property could be used to reduce the increase of the latency by pre-calculating method. The proposed architectures can be used in the IC design of high-speed optical communication systems.

关 键 词：光通信 BCH码 Berlekamp—Massey算法 流水线设计 

分 类 号：TN492[电子电信—微电子学与固体电子学]