无铅倒装焊封装工艺中的芯片应力及开裂分析  

Die Stress and Cracking Analysis of Lead-free Solder in Flip Chip Packages

作　　者：潘宏明[1] 杨道国[1] 罗海萍[1] 李宇君[1] 

机构地区：[1]桂林电子工业学院机电与交通工程系,广西桂林541004

出　　处：《电子元件与材料》2006年第9期57-59,共3页Electronic Components And Materials

基　　金：国家自然科学基金资助项目(60166001)

摘　　要：采用粘塑性Garofalo-Arrhenius模型描述无铅焊料的非弹性力学行为,确定了Sn3.5Ag焊料该模型的材料参数。采用与固化过程相关的粘弹性力学模型描述倒装焊底充胶的力学行为。利用有限元仿真的方法,模拟了无铅倒装封装器件封装的工艺及可靠性测试。结果表明:由于无铅技术在封装中的引入,芯片破裂的可能性随之增加,破裂出现时裂纹的尺寸更小。The viscoplastic Garofalo-Arrhenius model was employed to represent the inelastic deformation behavior of lead-free solders. The material parameters of Garofalo-Arrhenius model for Sn3.SAg solder was determined. A cure-dependent viscoelastic model was applied to describe the mechanical behavior of underfill. In addition, the stress/strain responses of lead-free Flip Chip on Board under packaging process and thermal cycling was simulated with finite element method. The results show that with lead-free technology applying, probability of die cracking probability increase. The defect size which will result in vertical cracking is greater.

关 键 词：半导体技术 无铅倒装焊 有限元仿真 封装工艺过程 芯片应力 开裂 

分 类 号：TN406[电子电信—微电子学与固体电子学]