一种新型高速低功耗BiC MOS分频器  

A Novel High-Speed Low-Power BiCMOS Frequency Divider

作　　者：李勇[1] 许永生[1] 赖宗声[1] 金玮[1] 陶永刚[1] 洪亮[1] 景为平[2] 

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200062 [2]南通大学专用集成电路设计重点实验室,江苏南通226007

出　　处：《电子器件》2006年第3期701-705,共5页Chinese Journal of Electron Devices

基　　金：国家自然科学基金项目资助(90407009);江苏省高技术研究项目资助(工业部分)(BG2005022);上海市科委资助(037062010);上海市AM基金资助(AM0308)

摘　　要：本文设计了一种基于BiCMOS技术的分频器,结合了双极(Bipolar)和CMOS技术的优点。作为分频器的基本单元,锁存器的工作速度直接影响了分频器的性能。通过分离跟踪差分对与交叉耦合对,并减小后者的偏置电流可以提高锁存器的工作速度。同时,合并两个锁存器的跟踪差分对可以减小分频器的功耗。采用0.8μm BiCMOS模型在CadenceSPECTRE中仿真,可以得到这种新型高速低功耗分频器的工作频率上限可以达到2.4 GHz,功耗为-1.61 dBm。A frequency divider based on BiCMOS technology is presented, which combines the merit of Bipolar with that of CMQS technology. Latch is the basic unit of frequency divider. The speed of latch has a direct effect on the performance of divider, which can be improved by separating trace differential pair and cross-coupled pair and decreasing the bias current of the later. The power of divider can be declined by means of combination of the trace differential pairs of these two latches. A novel high-speed low-power BiCMOS frequency divider provides higher speed for maximum frequency up to 2. 4 GHz and power of -1. 61 dBm, simulated in Cadence SPECTRE with 0. 8 μm BiCMOS model.

关 键 词：BICMOS 触发式分频器 跟踪差分对 交叉耦合对 跟踪模式 锁存模式 

分 类 号：TN433[电子电信—微电子学与固体电子学]