基于FPGA的APF控制器的硬件结构优化  

Hardware Architecture Optimization for FPGA Based Active Power Filter Controller

作　　者：舒泽亮[1] 郭育华[1] 连级三[1] 

机构地区：[1]西南交通大学电气工程学院,四川省成都市610031

出　　处：《电力系统自动化》2006年第18期55-60,共6页Automation of Electric Power Systems

摘　　要：提出一种基于现场可编程门阵列(FPGA)的并联型有源电力滤波器(SAPF)的控制器方案。通过简化算法,使用运算强度简化、折叠结构和流水线等方式优化了控制器的硬件结构和工作频率,并详细讨论了基于同步旋转坐标变换、无限冲击响应(ⅡR)低通滤波器、三相锁相环和滞环电流跟踪控制的结构设计与优化。全部控制算法在单片FPGA中用硬件描述语言VerilogHDL实现。样机实验结果表明系统的动静态性能都较好,满足高性能SAPF对控制器实时性和准确性的要求。A digital hardware control scheme of shunt active power filter （SAPF） based on field programmable gate arrays （FPGA） is introduced. Several strategies, such as algorithmic strength reduction, folded architecture and pipline method, are addressed to optimize hardware architecture and system operating frequency. An efficient controller including synchronous reference frame theory based distortion detection, infinite impulse response （IIR） low-pass filter, three-phase phase-locked loop （PLL）, and hysteresis current controller is designed. The entire control scheme of SAPF is developed on a single FPGA using VerilogHDL. Experimental results achieved from a prototype show the steady state and dynamic performance of the SAPF system with real-time and accurate control.

关 键 词：并联型有源电力滤波器 同步旋转坐标变换 IIR低通滤波器 三相锁相环 FPGA 

分 类 号：TM571[电气工程—电器]