面向芯片计算机集成的时钟树构建  

Construction of clock tree oriented to computer integration of chip

作　　者：石文兰[1] 南国芳[2] 李俊婷[1] 

机构地区：[1]河北工业职业技术学院信息工程与自动化系,河北石家庄050091 [2]天津大学系统工程研究所,天津300072

出　　处：《计算机集成制造系统》2006年第9期1459-1465,1482,共8页Computer Integrated Manufacturing Systems

摘　　要：阐述了芯片的版图设计中形成时钟二叉树的多级遗传算法,从理论上说明了该遗传算法的求解思路、编码方式、适应度函数、遗传算子的设计等。重点讨论了节点合并策略和单节点二叉树的形成。提出了时钟二叉树的多级模型,并设计了基于多级遗传算法的时钟二叉树形成算法。用该算法对随机测试例子和标准标杆测试例子的测试中发现,与传统的启发式算法相比,多级遗传算法能产生更好的测试结果。A kind of multi-level model of clock binary tree and its construction algorithm of clock signal based on multi-level genetic algorithm were proposed. Resolution methods, fitness function and design of genetic operator of the proposed genetic algorithm were theoretically expatiated. Node merge strategy and formation of single node binary tree were discussed in particular. From the results of random test cases and standard benchmark test cases by this algorithm, it could be concluded that multi-level genetic algorithm could produce much better test results compared with traditional heuristic algorithms.

关 键 词：二叉树 时钟布线 遗传算法 多级模型 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]