基于轮询机制的Utopia接口设计与实现  

Design and Implementation of Utopia Interface Based on Polling Mechanism

作　　者：马上[1] 陈红艳[1] 

机构地区：[1]西南科技大学信息工程学院,四川绵阳621010

出　　处：《西南科技大学学报》2006年第3期45-48,共4页Journal of Southwest University of Science and Technology

摘　　要：针对多个物理层传输芯片(PHY)、单ATM层的应用情况,分析了Utop ia level 2接口时序,基于现场可编程门阵列(FPGA)设计并实现了轮询机制的Utop ia接口逻辑,给出了时序仿真结果。设计了一种ATM同高层协议的接口逻辑并给出了进一步减小轮询操作开销的方法。同传统单端口模式相比,节约了75%的逻辑资源和引脚。测试结果表明,4个物理层单元能以155 Mbps的速度双向并行通信,可为模块化设计提供参考。According to the application of 1-ATM-muhi-PHY, the time sequence and function of Utopia interface level 2 is introduced. Polling logic of Utopia interface is designed and implemented based on field programmable gate array （FPGA）. The timing simulating results are provided. The method of interfacing with high layer and reducing overhead is proposed. 75% hardware resource of FPGA is saved compared with single port mode. Four PHYs can work at 155Mbps and the module designed can be a reference for designing Utopia interface.

关 键 词：ATM UTOPIA接口 现场可编程门阵列(FPGA) 轮询机制 状态机 

分 类 号：TN915.6[电子电信—通信与信息系统]