一种新型低kickback噪声的闩锁型比较器(英文)  

A Novel Latched Comparator with Low Kickback Noise

作　　者：张信[1] 于敦山[1] 盛世敏[1] 

机构地区：[1]北京大学信息科学技术学院微电子研究所,北京100871

出　　处：《北京大学学报（自然科学版）》2006年第5期681-684,共4页Acta Scientiarum Naturalium Universitatis Pekinensis

摘　　要：提出了一种新的闩锁型比较器结构。由于它的低kickback噪声特性,此比较器特别适合应用于差分模拟-数字转换器(ADCs)。电路采用标准0·35μm的工艺进行模拟,结果显示此比较器在3.3V电源下采样频率为400Ms/s,并且kickback噪声比传统结构减少了88%。A new latched comparator architecture was proposed. Because of its very low kickback noise feature, it is especially suitable for differential analog-to-digital converters （ADCs）. Simulated results of the proposed circuit in a 0.35 μm standard CMOS technology show that this comparator achieves a sampling speed of 400 Ms/s at 3.3-V supply, with a kickback noise 88% lower than conventional schemes.

关 键 词：模拟-数字转换 平行ADC 高速比较器 kickback噪声 

分 类 号：TN792[电子电信—电路与系统]