一个用于流水线模数转换器的高精度、低功耗采样保持电路  

A High Resolution Low Power Sample and Hold Module Dedicated to a Pipelined ADC

作　　者：金锐[1,2] 张天义[1,2] 杨鑫[1,2] 

机构地区：[1]北京大学深圳研究生院,深圳518055 [2]北京大学微电子系,北京100871

出　　处：《北京大学学报（自然科学版）》2006年第5期685-689,共5页Acta Scientiarum Naturalium Universitatis Pekinensis

摘　　要：介绍了一个用于高精度模数转换器,采用0·25μmCMOS工艺的高性能采样保持电路。该采样保持电路的采样频率为20MHz,允许最大采样信号频率为10MHz,在电源电压为2·5V的情况下,采样信号全差分幅度为2V。通过采用全差分flip-around结构,而非传统的电荷传输构架,因而在同等精度下,大大降低了功耗。为了提高信噪比,采用自举开关。Hspice仿真结构显示:在输入信号为5MHz的情况下,无杂散动态范围(SFDR)为92·4dB.该电路将被用于一个14位20MHz流水线模数转换器。A high performance sample-and-hold（S/H） circuit dedicated to a high resolution analog to digital converter is designed and implemented in 0.25 μm CMOS process. The sampling rate of this proposed S/H module is 20 MHz with a bandwidth of 10 MHz, the full scale of the sampled fully differential signal is 2 V with the 2.5 V power supply. Instead of the traditional charge transfer architecture, a fully differential flip-around architecture is used to reduce the power consumption. In order to improve the signal to noise ratio（SNR）, a bootstrapped switch is implemented in two places. Hspice simulation shows that it achieves a SFDR of 92.4 dB for 5 MHz input signal. This circuit is integrated to one 14-bit 20 MHz pipelined ADC.

关 键 词：采样保持 模数转换器 自举开关 增益增强放大器 

分 类 号：TN792[电子电信—电路与系统]