基于试验设计技术的IC可靠性优化设计  

Based on DOE Technology IC Reliability Optimization Design

作　　者：罗劲峰[1] 游海龙[2] 

机构地区：[1]华中光电技术研究所,武汉430074 [2]西安电子科技大学微电子学院,西安710071

出　　处：《电子质量》2006年第10期28-30,共3页Electronics Quality

摘　　要：现代IC设计对设计者提出了更多要求,不仅要求电路满足特定功能,而且还需要满足高质量和可靠性的要求。集成电路可靠性设计的目标是使性能对不可控因素不敏感,仅依靠EDA仿真很难完成这类设计。本文探讨了利用响应曲面(RSM)统计试验设计(DOE)与电路仿真相结合对集成电路进行可靠性优化设计的方法。并将该方法应用于电压带隙基准电路可靠性优化设计。优化确定的参数组合在满足电路指标同时,对温度的变化更加不敏感,提高了电路的可靠性要求。The modern IC design requires the circuit meet the both of the function and high reliability. The object of the IC reliability design makes the performances insensitive to uncontrollable factor, for example variation in temperature. It can not be achieved only to rely on the EDA simulation.The method is discussed that using DOE combined with EDA simulation optimizes and design the band-gap voltage reference circuits for reliability. Based on the model the circuit is optimized for reliability. The optimized parameter sets satisfying the design targets make the circuit output is more insensitive to the temperature variation.

关 键 词：可靠性 试验设计 电压带隙基准 

分 类 号：TN402[电子电信—微电子学与固体电子学]