分组密码的硬件实现  

Hardware implementation of block cipher algorithm

作　　者：唐明[1] 汪波[2] 杨欣[2] 张焕国[1] 

机构地区：[1]武汉大学计算机学院,武汉430079 [2]湖北经济学院,武汉430205

出　　处：《哈尔滨工业大学学报》2006年第9期1558-1562,共5页Journal of Harbin Institute of Technology

基　　金：国家自然科学基金资助项目(66973034;90104005;60373087);国家高技术研究发展计划资助项目(2002AA141051);教育部博士点基金资助项目(20020486046)

摘　　要：从硬件设计角度提出对分组密码设计的要求。通过对R ijndael算法的分析得到分组密码算法的通用运算部件,分别从提高速度和降低成本两方面逐一分析各部件的硬件实现方法同时考虑了芯片资源的分布特点.论文最后通过对R ijndael算法高速度和低成本两种实现方法的具体参数对比,提出面向硬件的分组密码设计.Some advices for block cipher algorithm from the point of hardware implementation have been given. After analyzing Rijndael algorithm, this paper concludes the common operations in block cipher algorithm and analyzes hardware implementation methods from two aspects of enhancing the speed and reducing the cost respectively and considers the hardware resources of FPGA chips. Finally, compared the results of high throughput with low cost designs, some properties of hardware implementation for block cipher algorithm are concluded.

关 键 词：分组密码 硬件设计 FPGA RIJNDAEL算法 

分 类 号：TP309[自动化与计算机技术—计算机系统结构]