一种低功耗10位流水线结构的CMOS A/D转换器的设计  

A CMOS 10-bit low-power pipelined A/D converter

作　　者：代国定[1] 刘锋[1] 庄奕琪[1] 

机构地区：[1]西安电子科技大学电路CAD研究所,陕西西安710071

出　　处：《电路与系统学报》2006年第5期17-20,共4页Journal of Circuits and Systems

摘　　要：本文设计了一种可满足视频速度应用的低电压低功耗10位流水线结构的CMOS A/D转换器。该转换器由9个低功耗运算放大器和19个比较器组成,采用1.5位/级共9级流水线结构,级间增益为2并带有数字校正逻辑。为了提高其抗噪声能力及降低二阶谐波失真,该A/D转换器采用了全差分结构。全芯片模拟结果表明,在3V工作电压下,以20MHz的速度对2MHz的输入信号进行采样时,其信噪失调比达到53dB,功率消耗为28.7mW。最后,基于0.6μm CMOS工艺得到该A/D转换器核的芯片面积为1.55mm2。An experimental low-voltage low-power 10-bit pipelined analog-to-digital converter for video-rate applications is presented in this paper. The 1.5b/stage architecture with digital correction is adopted in this pipelined ADC. It consists of 9 stages in which only 19 comparators and 9 low-power operational amplifiers are needed. Fully-differential structure is used to increase the noise immunity and reduce 2nd order harmonic distortion. The ADC achieves a signal-to-noise-and-distortion of 53dB for whole-chip simulation with 2MHz input sampled at 20Msamples/s, consuming 28.7mW. It is implemented in 0.6μm CMOS technology with a core area of 1.55mm^2.

关 键 词：A/D转换器 流水线结构 低功耗运算放大器 

分 类 号：TN792[电子电信—电路与系统]