数域筛法中线性代数的硬件设计  

Hardware Designs for Linear Algebra of Number Field Sieve

作　　者：刘海波[1] 王新梅[1] 

机构地区：[1]西安电子科技大学综合业务网国家重点实验室,陕西西安710071

出　　处：《计算机应用研究》2006年第11期52-55,共4页Application Research of Computers

基　　金：国家自然科学基金资助项目(60272057)

摘　　要：近来,针对数域筛法分解大数算法中线性代数步骤提出了几种硬件设计方案。对这些硬件设计,总结了其实现思想,描述了具体实现过程,分析了它们的优缺点,给出了实现费用和时间。随着设计的不断更新和完善,硬件设计的可行性不断提高,“费用×时间”函数不断降低,但是上升到具体实现仍有待于更深入的研究。Recently ,a few hardware designs were proposed for the linear algebra step of the number field sieve integer factoring algorithm, This paper summarizes their realization thought, describes their concrete realization process, analyses their advantage and disadvantage, presents their realization cost and time, Following the continued updating and consummating, the feasibility and the ＂cost× time＂ function of hardware device are better and better, but it need more effort to concretely realize.

关 键 词：RSA 分解 数域筛法 线性代数步骤 硬件设计 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]