FPGA布线通道分布对面积效率的影响研究  

The Research of Area-Efficiency for the Routing Channel Distribution in FPGAs

作　　者：徐新民[1] 王倩[1] 严晓浪[2] 

机构地区：[1]浙江大学电子电路与信息系统研究所,杭州310027 [2]浙江大学超大规模集成电路设计研究所,杭州310027

出　　处：《电子与信息学报》2006年第10期1959-1962,共4页Journal of Electronics & Information Technology

摘　　要：该文提出了现场可编程门阵列(FPGA)布线通道不均匀分布对芯片面积的影响。引入几个典型的数学分布函数(高斯,正弦和三角分布),实现通道容量随函数分布变化的新FPGA结构。将这些结构的FPGA与传统的布线通道均匀分布的FPGA作比较,结果表明按照数学分布变化的布线通道分布结构比均匀分布情况下的面积效率要高。亦即通道分布的变化趋势是峰值位置位于芯片中央,即通道容量最大,从中间位置向边缘按函数变化趋势逐渐变小。The effect of track distribution on chip area is investigated in this paper. Several typical distributions in math （Gaussian, Sine and Trigonal） are introduced to realize FPGAs architectures with routing channel width varying randomly on software platform. These various kinds of FPGA architecture are made comparison to the traditional FPGA with uniform routing channel width. The key results are that the non-uniform routing architectures educed from the introduction of math＇s distribution have a better area efficient than the uniform ones without sacrificing the circuit speed. And the trend of routing channel width transformation is that in the center of the chip is the peak point, and from the center to the edges the channel width becomes narrow gradually.

关 键 词：FPGA 布线 通道容量 轨道 高斯分布 

分 类 号：TN402[电子电信—微电子学与固体电子学] TN403