基于流水线CORDIC算法的数字下变频实现  

Implementation of DDC Based on Pipelined CORDIC Algorithm

作　　者：郑瑾 葛临东[2] 

机构地区：[1]北京市947信箱7分箱,北京100083 [2]解放军信息工程大学,郑州450002

出　　处：《现代雷达》2006年第10期62-64,共3页Modern Radar

摘　　要：数字下变频的FPGA实现通常都是基于查表的方法,为了达到高精度要求,常常需要耗费大量的ROM资源去建立庞大的查找表。文中提出了一种基于流水线CORDIC算法的数字下变频实现方案,可有效地节省FPGA的硬件资源,提高运算速度。文章最后给出了该方案的精度分析和实验的仿真结果。The common approach to implement DDC （ Digital Down Conversion ） on FPGA is based on a look-up table, which requires a huge volume of ROM to achieve high resolution. This paper porposes a pipelined architecture for implementation of DDC on FPGA, which, based on CORDIC algorithm, can save considerable hardware resources and improve the speed performance as well. Finally, a quantization error analysis and simulation results are presented.

关 键 词：数字下变频 CORDIC算法 流水线 FPGA芯片 

分 类 号：TN791[电子电信—电路与系统]