32位多线程包处理微引擎的设计  

Design of a 32-bit Multi-Thread Packet Processing Micro-Engine

作　　者：周昔平[1] 高德远[1] 樊晓桠[1] 张盛兵[1] 

机构地区：[1]西北工业大学航空微电子中心,陕西西安710072

出　　处：《小型微型计算机系统》2006年第11期2072-2076,共5页Journal of Chinese Computer Systems

基　　金：国防"十五"预研课题项目(41308010307)资助.

摘　　要：硬件多线程技术是网络处理器中的核心技术.本文介绍了一个专门面向网络协议处理的硬件多线程包处理微引擎NRS05的设计.详细介绍了其流水线的整体结构,提出了一种基于混合多线程的动态调度策略实现了长延时操作的隐藏,保证单线程性能能够满足应用需求的同时保证了各线程在执行核上运行的公平性.并将多线程技术和流水线技术进行了结合,解决了传统处理器中指令间因控制相关导致的流水线停顿问题.最后给出了设计的综合结果及包处理性能.Thread level parallel processing is one of the most important problems for high speed packet processing. This paper proposed a packet processing engine architecture called NRS05, that promotes the efficient dynamic thread scheduling for hiding long latency operations and coping with pipeline stalls. A dynamic thread scheduling scheme is presented by a mixedgrained multi-thread mechanism. Not only the performance of single packet processing is satisfied, but also the processor occupation probability for all threads are the same. And then data dependence and control dependence resolving methods and zero overhead context switching mechanism are also included. Finally this micro-engine is synthesized and verified, and the results suggest that the architecture of NRS05 is an attractive prospect for use in packet processing.

关 键 词：多线程 微引擎 动态线程调度 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]