嵌入式处理器中降低Cache缺失代价设计方法研究  

Research on Reducing Cache Miss Penalty of Embedded Processor

作　　者：黄海林[1] 许彤[1] 范东睿[1] 唐志敏[1] 

机构地区：[1]中国科学院计算技术研究所系统结构部

出　　处：《小型微型计算机系统》2006年第11期2077-2081,共5页Journal of Chinese Computer Systems

基　　金：中国科学院知识创新工程项目高性能通用CPU芯片研制(KGCX2-109);中国科学院知识创新重大项目高性能通用CPU芯片研制(KGCX1-SW-09)

摘　　要：以龙芯1号处理器为研究对象,探讨了嵌入式处理器中降低Cache缺失代价的设计方法.通过分析处理器的结构特征,本文实现了在关键字优先基础上一次缺失下命中的非阻塞数据Cache,可以将处理器平均性能提高3.9%.同时利用局部性原理,在关键字优先非阻塞数据Cache的基础上,本文提出了一种类非阻塞的指令Cache设计方法,可以降低指令Cache的缺失代价,以较小的实现代价进一步将处理器平均性能提高7.7%.通过本文的工作,可以同时降低指令Cache和数据Cache的缺失代价,处理器的平均性能提高了11.6%.With godson-1 processor as the research prototype,a real chip developed by ICT-CAS, this paper is focused on the design methodology of reducing cache miss penalty of embedded processor. By analyzing the processor architecture ,a hit-under- one-miss non-blocking data cache based on critical-word-prior technique is implemented,and the processor performance is improved 3.9 %. At the same time a hit-under-one-miss non-blocking-alike instruction cache technique is presented to reduce the instruction cache miss penalty,and the processor performance is improved 7.7%. Both data cache and instruction cache miss penalty is reduced significantly by the methodology presented in this paper at the same time, and total 11.6% processor performance improvement is achieved.

关 键 词：嵌入式处理器 CACHE 缺失代价 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]