0.25μm CMOS工艺10位100MHz流水线型ADC设计  

Design of a 10-bit 100MHz Pipelined ADC Using 0.25μm CMOS Process

作　　者：姜申飞[1] 戴庆元[1] 朱红卫 陈美娜[1] 王冬辉[1] 

机构地区：[1]上海交通大学微纳科学技术研究院,上海200030 [2]上海华虹NEC电子有限公司,上海201203

出　　处：《半导体技术》2006年第11期835-838,共4页Semiconductor Technology

摘　　要：采用流水线结构完成了一个10位精度100MHz采样频率的模数转换器的设计。该模数转换器采用采样保持电路、8级1.5位和最后一级2位子模数转换器的结构,电路使用全差分和开关电容电路技术。芯片采用台积电(TSMC)0.25μmCMOS工艺,电路典型工作电压为2.5V,在室温下,输入信号为5MHz,采样频率100MHz时信号噪声失真比为59.7dB。A 10-bit, 100 Msamples/s pipelined ADC was presented. It was composed of a sample-and-hold circuit, eight stages with 1.5bit per stage, and a 2 bit flash ADC as last stage. Fully differential structure and switched capacitor technology were used. The ADC＇s design was based on the TSMC 0.25 μm, mixed signal process. It works at 2.5V supply voltage, at room temperature, 5 MHz input frequency and 100MHz sampling frequency, SNDR is 59.7dB.

关 键 词：流水线 模数转换器 采样保持 

分 类 号：TN432[电子电信—微电子学与固体电子学]