CPLD Implementation of 1024-Point FFT of Short-Wave Wideband Channel Simulator  

作　　者：GAN Liangcai DING Yahui LI Yuanyuan 

机构地区：[1]College of Electronic Information, Wuhan University, Wuhan 430079, China

出　　处：《Chinese Journal of Electronics》2006年第4期692-696,共5页电子学报（英文版）

基　　金：This work is supported by the National Natural Science Foundation of China （No.69772015, No.60372056）.

摘　　要：The method and implementation of 1024- point FFT of Short-wave （SW） wideband channel is introduced in this paper. Considered as a real-time Finiteimpulse-response （FIR） filter, SW channel can be implemented by Complex programmable logic device （CPLD）. In this design, SW wideband channel simulator was realized by Fast Fourier transform （FFT） based on radix-2 Decimation in time （DIT） algorithm, whose bandwidth was 1.536MHz and frequency interval was 3kHz. By four simple and effective operation units and the excellent structure of CPLD, the execution time of 1024-point FFT was 0.35ms when the global clock was 30.72MHz. The speed of calculation could be improved by faster clock. The result showed that the hardware implementation was feasible and flexible, and most of conditions of SW channel could be simulated precisely by changing the channel transfer function memorized in RAM. What＇s more, initial frequency table of frequency management system of SW channel could be set up by processing the outcome of FFT easily, which was used to analyse the performances of SW channel and to ensure the quality of communication.

关 键 词：SW channel Fast Fourier transform （FFT） Complex programmable logic device （CPLD） Frequency management system. 

分 类 号：TN791[电子电信—电路与系统]