用FPGA实现GPS的C/A码发生器  

Implementation of C/A code generator in GPS with FPGA

作　　者：王伟权[1] 刘昌孝[1] 

机构地区：[1]电子科技大学科学技术研究院,成都610054

出　　处：《桂林电子科技大学学报》2006年第5期347-350,共4页Journal of Guilin University of Electronic Technology

基　　金：全球定位系统项目

摘　　要：采用了FPGA方法来模拟高动态(G loba l Pos ition System GPS)信号源中的C/A码产生器。C/A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用,根据文献[1]引入C/A码生成方程,通过硬件描述语言VER ILOG在ISE中实现电路生成,采用M ODELS IM、SYNPL IFY工具分别进行仿真和综合。最后由图3展示的结果与文献[1]相对比证明了设计的正确性。FPGA has been used as a design method in the simulation of C/A code generator in high dynamic GPS. C/A code plays an important part in realising code division, coarse acquisition of satellite signal and acquisition of precise code （p code） with HOW（Handover Word）. In light of literature[1], C/A code is employed to generate equations. The circuit is realized with software ISE in VERILOG HDL （Hardware description language）. The program is simulated and synthesized with MODESIM and SYNPLIFY respectively. A comparison between the results from figure 3 and those of literature[1] indicates the correctness of the design proposed in this paper.

关 键 词：GPS C/A码 M序列 FPGA 

分 类 号：TN914.42[电子电信—通信与信息系统]