完全基于绝热电路的静态随机存储器(SRAM)设计  

Static random access memory(SRAM) design based on adiabatic circuits

作　　者：王芳[1] 兰景宏[1] 吉利久[1] 

机构地区：[1]北京大学微电子学研究所,北京100871

出　　处：《清华大学学报（自然科学版）》2006年第10期1747-1750,共4页Journal of Tsinghua University(Science and Technology)

摘　　要：为了降低静态随机存储器(SRAM)的功耗,提出了一种完全采用绝热电路实现的W A SRAM(W ho le A d iabaticSRAM),W A SRAM的译码部分、存储单元、读出放大等全部采用绝热电路结构。针对W A SRAM建立了功耗分析模型。基于0.18μm 1.8 V CM O S工艺,在不同频率下针对不同存储规模的SRAM进行了功耗仿真、分析和比较。实验结果证明,W A SRAM的低功耗效果十分明显,与传统CM O S电路实现的SRAM相比,在250 MH z频率下,W A SRAM功耗降低了80%以上。As a size of static random access memory （SRAM） design increases, the power also increases. This paper presents an SRAM design based on adiabatic circuits with all parts of the SRAM, including the decoder, cell, and sensor, designed with adiabatic circuits. A power model is presented for the SRAM design with various memory sizes simulated for various frequencies using 0. 18 μm 1.8 V CMOS technology. Experimental results show that the power of the adiabatic SRAM is substantially reduced. The power is reduced by more than 80% at 250 MHz.

关 键 词：SRAM 绝热电路 功耗分析 低功耗 

分 类 号：TN492[电子电信—微电子学与固体电子学]