基于多阈值技术的CMOS低功耗可预置边沿触发器设计  

Design of CMOS low-power pre-settable edge-triggered flip-flop based on multithreshold technique.

作　　者：沈继忠[1] 张华军[1] 张慧熙[1] 

机构地区：[1]浙江大学信息与电子工程学系,浙江杭州310028

出　　处：《浙江大学学报（理学版）》2006年第6期646-649,共4页Journal of Zhejiang University（Science Edition）

基　　金：浙江省自然科学基金资助项目(Y104368)

摘　　要：超大规模集成电路设计工艺已进入深亚微米阶段,漏电流功耗已经成为不可忽视的部分.多阈值CMOS技术是一种降低电路漏电流功耗的有效方法.它通过接入高阈值MOS管来抑制低阈值模块的漏电流.本文利用多阈值技术实现电路的冗余抑制,设计了基于多阈值技术的CMOS可预置主从型单边沿、双边沿D触发器.模拟结果表明,设计的触发器能有效降低电路漏电流功耗,跟已有文献提出的可预置主从型触发器相比,可节省近15%的功耗.As the process for design of VLSI enters deep submicron stage, the power dissipation caused by leakage current can not be neglected anymore. An effective way to reduce the leakage power is by means of multithreshold CMOS technique, which can restrain the leakage current by adding a MOS transistor to low threshold circuit. Redundancy of CMOS circuits can be restrained by muhithreshold CMOS, new pre-settable master-slave single-edgetriggered and double-edge-triggered D flip-flop based on multithreshold technique were designed. The results of simulations suggested that the designed flip-flops reduce the leakage power and save about 15% as compared with the flip-flops which were presented by other references.

关 键 词：CMOS多阈值 低功耗 漏电流 D触发器 

分 类 号：TP331.2[自动化与计算机技术—计算机系统结构]