Viterbi解码器RTL级设计优化  

Optimization of Architecture for Viterbi Decoder on RTL Design Stage

作　　者：喻希[1] 

机构地区：[1]同济大学通信软件及专用集成电路设计中心,上海200092

出　　处：《现代电子技术》2006年第23期137-139,142,共4页Modern Electronics Technique

摘　　要：当今芯片产业竞争激烈,速度低、面积大、功耗高的产品难以在市场中占有一席之地。Viterbi解码器作为一种基于最大后验概率的最优化卷积码解码器,被广泛应用于多种数字通信系统中,却由于其较高算法复杂程度,给芯片设计带来了挑战。针对芯片的速度、面积和功耗,通过对Viterbi解码器RTL级设计的若干优化方法进行研究和讨论,实现了一个应用于DVB-S系统的面积约为2万门的Viterbi解码器。Nowadays since the fierce competition in IC industry,low speed, big area or high power dissipation products can hardly take their places in the market. Viterbi decoder,as a kind of optimal decoding for convolutional codes based on Maximum- Likelihood （ML） criterion,is widely used in many digital communication systems, but brings challenges to the chip design because of its high algorithm complexity. This paper discusses several methods of optimization of architecture for Viterbi decoder on RTL design stage focusing primarily on speed,area and power dissipation of the chip,and a Viterbi decoder which is applied in DVB - S system with an area of about 2000 gates is implemented.

关 键 词：卷积码 VITERBI解码器 寄存器传输级 数字通信系统 

分 类 号：TN764[电子电信—电路与系统]