高性能CMOS全加器设计  

Realization of a High Performances CMOS Full-Adder

作　　者：吕虹[1] 徐慜 刘雨兰[1] 

机构地区：[1]安徽工程科技学院电气工程系 [2]上海通谷信息有限责任公司

出　　处：《电子测量与仪器学报》2006年第5期85-88,共4页Journal of Electronic Measurement and Instrumentation

基　　金：安徽省自然科学基金项目(编号:050420203);安徽省教育厅自然科学基金项目(编号:KJ2004064)。

摘　　要：全加器是数字信号处理器、微处理器中的重要单元,它不仅能完成加法,还能参与减法、乘法、除法等运算,所以,提高全加器性能具有重要意义。本文分析了两种普通全加器,运用布尔代数对全加器和函数、进位函数进行全面处理,提取了和函数、进位函数优化函数式。根据最优化函数式,设计了高性能CMOS管级全加器单元电路。这种CMOS全加器电路与常用CMOS全加器电路相比,电路结构简单、芯片面积小、电路传输延迟时间小、运算速度快。Full adders are important components in applications such as digital signal processors and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division, etc. So enhancing the performances of the 1-bit full adder cell is a significant goal. This paper analyzed two commonly static complementary CMOS full adders cell and presents a new improved 26-transistors static complementary CMOS full adder cell by optimizing the sum and carry functions of the full adder. Simulation on the full adder cells have demonstrated that the performances of 26-transistors static complementary CMOS full adder cell are enhanced when compared to the commonly full adder cells, which speed is increased and transistors counts is decreased. This cell is beneficial to improve performances of the overall system based on full adder cell such as DSP,ALU ,MPU... etc.

关 键 词：CMOS 全加器 布尔代数 优化函数式 传输延迟时间 芯片面积 

分 类 号：TN401[电子电信—微电子学与固体电子学]