Test Time Minimization for Hybrid BIST of Core-Based Systems  

Test Time Minimization for Hybrid BIST of Core-Based Systems

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作  者:Gert Jervan Petru Eles Zebo Peng Raimund Ubar Maksim Jenihhin 

机构地区:[1]Embedded Systems Laboratory (ESLAB), Linkoeing University, Sweden [2]Department of Computer Engineering, Tallinn University of Technology, Estonia

出  处:《Journal of Computer Science & Technology》2006年第6期907-912,共6页计算机科学技术学报(英文版)

基  金:Supported by the Estonian Science Foundation grants G6829 and G5910, Enterprise Estonia project Technology Development Centre ELIK0, and the Swedish Foundation for Strategic Research (SSF) under the Strategic Integrated Electronic Systems Research (STRINGENT) program.

摘  要:This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach cmploys a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.This paper presents a solution to the test time minimization problem for core-based systems. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off-line and stored in the system. In this paper we propose an iterative algorithm to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach cmploys a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions.

关 键 词:SoC SELF-TEST hybrid BIST 

分 类 号:TP3[自动化与计算机技术—计算机科学与技术]

 

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