TTA结构数字信号协处理器数据Cache的设计与实现  

Design and Implement of Data Cache for Digital Signal Coprocessor Based on TTA

作　　者：姜晶菲[1] 郭建军[1] 戴葵[1] 王志英[1] 

机构地区：[1]国防科学技术大学计算机学院,长沙410073

出　　处：《计算机工程与应用》2006年第33期8-10,19,共4页Computer Engineering and Applications

基　　金：国家自然科学基金资助项目(90407022)

摘　　要：论文分析了面向多媒体应用的TTA(TransportTriggeredArchitecture)微处理器的特点和访存要求,提出并设计实现了应用于此款微处理器、采用直接映象规则、写回和按写分配策略的4KB数据Cache,并在全系统环境下对其进行了模拟验证。实验结果说明数据Cache系统在降低命中时间和提高命中率两方面做到了良好的折中,命中时间与芯片流水线处理周期匹配,有效保证了全系统性能的发挥。The characteristics of Transport Triggered Architecture（TTA） have been analyzed.The excellent process ability of TTA pipeline gave high demands to the data cache,A 4 KB data cache system which used direct mapped principle, write back and write allocate strategies has been proposed and implemented.The data cache combined with the TTA pipeline and other function units compose the whole TTA microprocessor,The microprocessor has been simulated completely with real applicatlons.The implementation results prove that the data cache in TTA microprocessor can achieve excellent trade-off for hit time and hit probability.The hit time can match the pipeline cycle and the high performance of the microprocessor is ensured.

关 键 词：TTA 数据CACHE 直接映象 写回 按写分配 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]