基于FPGA的H.264变换量化的高性能的硬件实现  

A High-performance Hardware Implementation of the H.264 Transformation and Quantization Oriented to FPGA

作　　者：刘海鹰[1] 张兆杨[1] 沈礼权[1] 

机构地区：[1]上海大学教育部新型显示技术及应用重点实验室,上海200072

出　　处：《中国图象图形学报》2006年第11期1636-1639,共4页Journal of Image and Graphics

基　　金：国家自然科学基金重点项目(60332030);上海市科委重点攻关项目(055115008)

摘　　要：针对H.264视频标准中一个功能频繁调用的变换量化模块,提出了一种高性能的FPGA硬件实现方法,并完成了其硬件原型的设计。该硬件原型包含了从残差形成到宏块重建的变换量化全过程,其可以构成DSP的协处理器,用于完成H.264实时编解码。该硬件原型根据算法特点和数据流特点,采用了流水线控制策略和分时复用技术,同时合理利用FPGA片内资源,从而提高了系统性能。仿真结果表明,该设计能满足高清数字视频的实时处理应用。This paper presents a high-performance FPGA hardware implementation of the H. 264 transformation and quantization. The hardware prototype is composed of the whole processes from obtaining residual error to Macro-Block reconstruction, and it can be used as a co-processor of DSP to fulfill H. 264 real-timing CODEC. Based on the characteristics of algorithms and data flow, the hardware prototype adopts pipeline strategy and time division multiplexing（TDM） technology, and utilizes FPGA dedicated resources reasonably, that enhances the performance of the hardware prototype greatly. The simulation results show that the design can satisfy the real-time constraints required by HDTV applications.

关 键 词：H.264 整数变换 分级量化 流水线 分时复用 

分 类 号：TN919.81[电子电信—通信与信息系统]