基于CPLD多路QAC的逻辑电路设计  

A design of logic circuit based on CPLD of multi-channel QAC

作　　者：李勇[1] 苏弘[1] 李素琴[1] 彭宇[1] 千奕[1] 

机构地区：[1]中国科学院近代物理研究所

出　　处：《核电子学与探测技术》2006年第6期824-827,共4页Nuclear Electronics & Detection Technology

摘　　要：主要介绍了多道电荷幅度转换器(QAC)的逻辑电路部分。包括积分控制电路和仲裁电路。用可程逻辑器件CPLD来构建这部分电路,和常规的逻辑器件相比其突出特点是:元件少、成本低、功耗低。并且在速度上完全可以替代ECL器件,适合于构建大型的逻辑电路。A circuit designed by us for charge to amplitude conversion （QAC） is introduced briefly in this paper, Its logic circuit is the emphasis in the article, which includes two parts： one is the control circuit of integrator, the other is the judgement circuit. We use CPLD to constitute the logic circuit. Compared with the ECL and TTL devices , It has features as follows： less components ,lower cost, lower dissipation. For its high speed , It can replace the ECL device. The CPLD is very suitable to constitute large digital circuit.

关 键 词：多路 QAC CPLD设计 

分 类 号：TN78[电子电信—电路与系统]