基于DA和专用累加器的高性能DCT结构  

High Performance DCT Architecture Based on DA and Special Accumulator

作　　者：郭向东[1] 赵峰[1] 

机构地区：[1]上海交通大学微电子学院,上海200030

出　　处：《微电子学》2006年第6期830-833,共4页Microelectronics

基　　金：国家高技术研究发展(863)计划"个人信息处理终端SoC"资助项目(2003AA1Z1350)

摘　　要：提出了一种基于分布式算法(DA)和专用累加器的高性能DCT结构。该专用累加器由32压缩器、42压缩器、条件和选择器(CSS)和超前进位加法器构成,可以在单周期内实现来自LUT的四个部分积的累加。文章提出的结构以50%的额外硬件资源,实现基于循环累加的传统DA结构8倍的数据处理速度。分析了不同运算精度的条件下,DCT结构在面积和速度上的优化。该DCT结构设计采用TSMC 0.18μm工艺库,其工作频率可达120 MHz,达到每秒480兆像素的处理能力。A new discrete cosine transform （DCT） architecture based on distributed arithmetic （DA） and an application specific accumulator is proposed. This special accumulator, which is comprised of 3-2 compressor, 4-2 compressor, conditional sum selector （CSS） and carry look-ahead adder （CLA）, implements multiplication by accumulating 4 partial products from lookup table （LUT） at one cycle. The proposed architecture achieves 8 times throughput rate of conventional DA based on shift-add with 50% extra hardware cost. The performance in trading off the area efficiency with less demands of data precision is also demonstrated. Designed in TSMC＇s 0. 18μm cell library, the architecture has an operation frequency up to 120 MHz.

关 键 词：离散余弦变换 分布式算法 条件和选择器 

分 类 号：TN303[电子电信—物理电子学]